Camcorder what is ccd

A single MOS device of this type is illustrated in Figure 2 , with reverse bias operation causing negatively charged electrons to migrate to an area underneath the positively charged gate electrode. Electrons liberated by photon interaction are stored in the depletion region up to the full well reservoir capacity. When multiple detector structures are assembled into a complete CCD, individual sensing elements in the array are segregated in one dimension by voltages applied to the surface electrodes and are electrically isolated from their neighbors in the other direction by insulating barriers, or channel stops , within the silicon substrate.

The light-sensing photodiode elements of the CCD respond to incident photons by absorbing much of their energy, resulting in liberation of electrons, and the formation of corresponding electron-deficient sites holes within the silicon crystal lattice. One electron-hole pair is generated from each absorbed photon, and the resulting charge that accumulates in each pixel is linearly proportional to the number of incident photons.

External voltages applied to each pixel's electrodes control the storage and movement of charges accumulated during a specified time interval. Initially, each pixel in the sensor array functions as a potential well to store the charge during collection, and although either negatively charged electrons or positively charged holes can be accumulated depending on the CCD design , the charge entities generated by incident light are usually referred to as photoelectrons.

This discussion considers electrons to be the charge carriers. These photoelectrons can be accumulated and stored for long periods of time before being read from the chip by the camera electronics as one stage of the imaging process. Image generation with a CCD camera can be divided into four primary stages or functions: charge generation through photon interaction with the device's photosensitive region, collection and storage of the liberated charge, charge transfer, and charge measurement.

During the first stage, electrons and holes are generated in response to incident photons in the depletion region of the MOS capacitor structure, and liberated electrons migrate into a potential well formed beneath an adjacent positively-biased gate electrode. The system of aluminum or polysilicon surface gate electrodes overlie, but are separated from, charge carrying channels that are buried within a layer of insulating silicon dioxide placed between the gate structure and the silicon substrate.

Utilization of polysilicon as an electrode material provides transparency to incident wavelengths longer than approximately nanometers and increases the proportion of surface area of the device that is available for light collection. Electrons generated in the depletion region are initially collected into electrically positive potential wells associated with each pixel. During readout, the collected charge is subsequently shifted along the transfer channels under the influence of voltages applied to the gate structure.

Figure 3 illustrates the electrode structure defining an individual CCD sense element. In general, the stored charge is linearly proportional to the light flux incident on a sensor pixel up to the capacity of the well; consequently this full-well capacity FWC determines the maximum signal that can be sensed in the pixel, and is a primary factor affecting the CCD's dynamic range. The charge capacity of a CCD potential well is largely a function of the physical size of the individual pixel.

Since first introduced commercially, CCDs have typically been configured with square pixels assembled into rectangular area arrays, with an aspect ratio of being most common. Figure 4 presents typical dimensions of several of the most common sensor formats in current use, with their size designations in inches according to a historical convention that relates CCD sizes to vidicon tube diameters. The rectangular geometry and common dimensions of CCDs result from their early competition with vidicon tube cameras, which required the solid-state sensors to produce an electronic signal output that conformed to the prevailing video standards at the time.

Note that the "inch" designations do not correspond directly to any of the CCD dimensions, but represent the size of the rectangular area scanned in the corresponding round vidicon tube. A designated "1-inch" CCD has a diagonal of 16 millimeters and sensor dimensions of 9. Although consumer cameras continue to primarily employ rectangular sensors built to one of the "standardized" size formats, it is becoming increasingly common for scientific-grade cameras to incorporate square sensor arrays, which better match the circular image field projected in the microscope.

A large range of sensor array sizes are produced, and individual pixel dimensions vary widely in designs optimized for different performance parameters. The maximum dimension represented by the diagonal of many sensor arrays is considerably smaller than the typical microscope field of view, and results in a highly magnified view of only a portion of the full field.

The increased magnification can be beneficial in some applications, but if the reduced field of view is an impediment to imaging, demagnifying intermediate optical components are required. The alternative is use of a larger CCD that better matches the image field diameter, which ranges from 18 to 26 millimeters in typical microscope configurations. An approximation of CCD potential-well storage capacity may be obtained by multiplying the diode pixel area by Using this approximation strategy, a diode with 10 x 10 micrometer dimensions will have a full-well capacity of approximately , electrons.

For a given CCD size, the design choice regarding total number of pixels in the array, and consequently their dimensions, requires a compromise between spatial resolution and pixel charge capacity. CCDs designed for scientific imaging have traditionally employed larger photodiodes than those intended for consumer especially video-rate and industrial applications.

Because full-well capacity and dynamic range are direct functions of diode size, scientific-grade CCDs used in slow-scan imaging applications have typically employed diodes as large as 25 x 25 micrometers in order to maximize dynamic range, sensitivity, and signal-to-noise ratio. Many current high-performance scientific-grade cameras incorporate design improvements that have enabled use of large arrays having smaller pixels, which are capable of maintaining the optical resolution of the microscope at high frame rates.

Large arrays of several million pixels in these improved designs can provide high-resolution images of the entire field of view, and by utilizing pixel binning discussed below and variable readout rate, deliver the higher sensitivity of larger pixels when necessary. Before stored charge from each sense element in a CCD can be measured to determine photon flux on that pixel, the charge must first be transferred to a readout node while maintaining the integrity of the charge packet.

A fast and efficient charge-transfer process, as well as a rapid readout mechanism, are crucial to the function of CCDs as imaging devices. When a large number of MOS capacitors are placed close together to form a sensor array, charge is moved across the device by manipulating voltages on the capacitor gates in a pattern that causes charge to spill from one capacitor to the next, or from one row of capacitors to the next.

The translation of charge within the silicon is effectively coupled to clocked voltage patterns applied to the overlying electrode structure, the basis of the term "charge-coupled" device. The CCD was initially conceived as a memory array, and intended to function as an electronic version of the magnetic bubble device. The charge transfer process scheme satisfies the critical requirement for memory devices of establishing a physical quantity that represents an information bit, and maintaining its integrity until readout.

In a CCD used for imaging, an information bit is represented by a packet of charges derived from photon interaction.

Because the CCD is a serial device, the charge packets are read out one at a time. The stored charge accumulated within each CCD photodiode during a specified time interval, referred to as the integration time or exposure time , must be measured to determine the photon flux on that diode. Quantification of stored charge is accomplished by a combination of parallel and serial transfers that deliver each sensor element's charge packet, in sequence, to a single measuring node.

The electrode network, or gate structure , built onto the CCD in a layer adjoining the sensor elements, constitutes the shift register for charge transfer.

The basic charge transfer concept that enables serial readout from a two-dimensional diode array initially requires the entire array of individual charge packets from the imager surface, constituting the parallel register , to be simultaneously transferred by a single-row incremental shift.

The charge-coupled shift of the entire parallel register moves the row of pixel charges nearest the register edge into a specialized single row of pixels along one edge of the chip referred to as the serial register. It is from this row that the charge packets are moved in sequence to an on-chip amplifier for measurement. After the serial register is emptied, it is refilled by another row-shift of the parallel register, and the cycle of parallel and serial shifts is repeated until the entire parallel register is emptied.

Some CCD manufacturers utilize the terms vertical and horizontal in referring to the parallel and serial registers, respectively, although the latter terms are more readily associated with the function accomplished by each.

A widely used analogy to aid in visualizing the concept of serial readout of a CCD is the bucket brigade for rainfall measurement, in which rain intensity falling on an array of buckets may vary from place to place in similarity to incident photons on an imaging sensor see Figure 5 a.

The parallel register is represented by an array of buckets, which have collected various amounts of signal water during an integration period. The buckets are transported on a conveyor belt in stepwise fashion toward a row of empty buckets that represent the serial register, and which move on a second conveyor oriented perpendicularly to the first. In Figure 5 b , an entire row of buckets is being shifted in parallel into the reservoirs of the serial register.

The serial shift and readout operations are illustrated in Figure 5 c , which depicts the accumulated rainwater in each bucket being transferred sequentially into a calibrated measuring container, analogous to the CCD output amplifier. When the contents of all containers on the serial conveyor have been measured in sequence, another parallel shift transfers contents of the next row of collecting buckets into the serial register containers, and the process repeats until the contents of every bucket pixel have been measured.

There are many designs in which MOS capacitors can be configured, and their gate voltages driven, to form a CCD imaging array.

As described previously, gate electrodes are arranged in strips covering the entire imaging surface of the CCD face. The simplest and most common charge transfer configuration is the three-phase CCD design, in which each photodiode pixel is divided into thirds with three parallel potential wells defined by gate electrodes.

In this design, every third gate is connected to the same clock driver circuit. The basic sense element in the CCD, corresponding to one pixel, consists of three gates connected to three separate clock drivers, termed phase-1, phase-2, and phase-3 clocks.

Each sequence of three parallel gates makes up a single pixel's register, and the thousands of pixels covering the CCD's imaging surface constitute the device's parallel register. Once trapped in a potential well, electrons are moved across each pixel in a three-step process that shifts the charge packet from one pixel row to the next. A sequence of voltage changes applied to alternate electrodes of the parallel vertical gate structure move the potential wells and the trapped electrons under control of a parallel shift register clock.

The general clocking scheme employed in three-phase transfer begins with a charge integration step, in which two of the three parallel phases per pixel are set to a high bias value, producing a high-field region relative to the third gate, which is held at low or zero potential.

For example, phases 1 and 2 may be designated collecting phases and held at higher electrostatic potential relative to phase 3, which serves as a barrier phase to separate charge being collected in the high-field phases of the adjacent pixel. Following charge integration, transfer begins by holding only the phase-1 gates at high potential so that charge generated in that phase will collect there, and charge generated in the phase-2 and phase-3 phases, now both at zero potential, rapidly diffuses into the potential well under phase 1.

Charge transfer progresses with an appropriately timed sequence of voltages being applied to the gates in order to cause potential wells and barriers to migrate across each pixel. At each transfer step, the voltage coupled to the well ahead of the charge packet is made positive while the electron-containing well is made negative or set to zero ground , forcing the accumulated electrons to advance to the next phase.

Rather than utilizing abrupt voltage transitions in the clocking sequence, the applied voltage changes on adjacent phases are gradual and overlap in order to ensure the most efficient charge transfer. The transition to phase 2 is carried out by applying positive potential to the phase-2 gates, spreading the collected charge between the phase-1 and phase-2 wells, and when the phase-1 potential is returned to ground, the entire charge packet is forced into phase 2.

A similar sequence of timed voltage transitions, under control of the parallel shift register clock, is employed to shift the charge from phase 2 to phase 3, and the process continues until an entire single-pixel shift has been completed. One three-phase clock cycle applied to the entire parallel register results in a single-row shift of the entire array.

An important factor in three-phase transfer is that a potential barrier is always maintained between adjacent pixel charge packets, which allows the one-to-one spatial correspondence between sensor and display pixels to be maintained throughout the image capture sequence. Figure 6 illustrates the sequence of operations just described for charge transfer in a three-phase CCD, as well as the clocking sequence for drive pulses supplied by the parallel shift register clock to accomplish the transfer.

In this schematic visualization of the pixel, charge is depicted being transferred from left to right by clocking signals that simultaneously decrease the voltage on the positively-biased electrode defining a potential well and increase it on the electrode to the right Figures 6 a and 6 b. In the last of the three steps Figure 6 c , charge has been completely transferred from one gate electrode to the next.

Note that the rising and falling phases of the clock drive pulses are timed to overlap slightly not illustrated in order to more efficiently transfer charge and to minimize the possibility of charge loss during the shift. With each complete parallel transfer, charge packets from an entire pixel row are moved into the serial register where they can be sequentially shifted toward the output amplifier, as illustrated in the bucket brigade analogy Figure 5 c.

This horizontal serial transfer utilizes the same three-phase charge-coupling mechanism as the vertical row-shift, with timing control provided in this case by signals from the serial shift register clock. After all pixels are transferred from the serial register for readout, the parallel register clock provides the time signals for shifting the next row of trapped photoelectrons into the serial register.

Each charge packet in the serial register is delivered to the CCD's output node where it is detected and read by an output amplifier sometimes referred to as the on-chip preamplifier that converts the charge into a proportional voltage. The voltage output of the amplifier represents the signal magnitude produced by successive photodiodes, as read out in sequence from left to right in each row and from the top row to the bottom over the entire two-dimensional array. The CCD output at this stage is, therefore, an analog voltage signal equivalent to a raster scan of accumulated charge over the imaging surface of the device.

After the output amplifier fulfills its function of magnifying a charge packet and converting it to a proportional voltage, the signal is transmitted to an analog-to-digital converter ADC , which converts the voltage value into the 0 and 1 binary code necessary for interpretation by the computer.

Each pixel is assigned a digital value corresponding to signal amplitude, in steps sized according to the resolution, or bit depth, of the ADC. Discover the best solutions to protect your business.

Group Policy and its Role. PoE Access Control. Wireless Access Control. Mobile Access Control Guide. We use cookies to enhance your experience and for marketing purposes. Read more. The larger the sensor, the more light it can capture, meaning it will produce better video in low light settings. Professional digital video cameras often have three sensors, referred to as "3CCD," which use separate CCDs for capturing red, green, and blue hues.

If you would like to reference this page or cite this definition, you can use the green citation links above. The goal of TechTerms. We strive for simplicity and accuracy with every definition we publish. If you have feedback about the CCD definition or would like to suggest a new technical term, please contact us. If you've read How Television Works , you know that a television "paints" images in horizontal lines across a screen, starting at the top and working downward.

TVs actually paint every other line in one pass this is called a "field" and then paint the alternate lines in the next pass. To create a video signal, a camcorder captures a frame of video from the CCD and records it as the two fields. The CCD actually has another sensor layer behind the image sensor.

For every field of video, the CCD transfers all the photosite charges to this second layer, which then transmits the electric charges at each photosite, one by one. In an analog camcorder, this signal goes to the VCR, which records the electric charges along with color information as a magnetic pattern on videotape.

While the second layer is transmitting the video signal, the first layer has refreshed itself and is capturing another image. A digital camcorder works in basically the same way, except that at this last stage an analog-to-digital converter samples the analog signal and turns the information into bytes of data 1s and 0s.

The camcorder records these bytes on a storage medium, which could be, among other things, a tape , a hard disk or a DVD. Most of the digital camcorders on the market today actually use tapes because they are less expensive , so they have a VCR component much like an analog camcorder's VCR.

Instead of recording analog magnetic patterns, however, the tape head records binary code. Interlaced digital camcorders record each frame as two fields, just as analog camcorders do.